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Infinite-ISP Image Signal Processing Pipeline FPGA Binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit.
Updated
Jun 10, 2024
Python
Squishy hardware design files
A small project I had in uni.
Updated
Jun 10, 2024
VHDL
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
Updated
Jun 10, 2024
VHDL
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
Updated
Jun 10, 2024
Verilog
A modern hardware definition language and toolchain based on Python
Updated
Jun 10, 2024
Python
Hardware Design/Visualization/Simulation/RTLGeneration Framework
Updated
Jun 10, 2024
Jupyter Notebook
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Updated
Jun 10, 2024
Assembly
Library implementing a common interface to manage FPGA tasks
Library implementing a common interface to manage FPGA memory and streams
Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑
Updated
Jun 10, 2024
Verilog
An experimental RISC-V Assembler web app built on Scala.js
Updated
Jun 10, 2024
Scala
State-of-the-art native debugging tool
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Amaranth HDL framework for laser scanner with motion control
Updated
Jun 10, 2024
Python
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Updated
Jun 10, 2024
Jupyter Notebook
building blocks for accelerating ZK proofs over binary fields
Updated
Jun 10, 2024
Verilog
Opensource DDR3 Controller
Updated
Jun 10, 2024
Verilog
An open-source HDL register code generator fast enough to run in real time.
Updated
Jun 10, 2024
Python
🕹 OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit
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