pw_cast_for_opmath for type promotion in torch.compile decompositions

[sujoysaraswati]

🐛 Describe the bug

Many ATen ops have the decorator pw_cast_for_opmath in torch/_decomp/decompositions.py, example -

@register_decomposition(aten.silu)
@out_wrapper()
@pw_cast_for_opmath
def silu(self: Tensor) -> Tensor:
    return self * torch.sigmoid(self)

This decorator applies a default type promotion for the ops, which doesn't occur in eager execution of the ops.

The following test case demonstrates this -

import torch._dynamo as dynamo
import torch

torch._dynamo.reset()

m = torch.nn.SiLU()

def toy_example(inp):
    out = m(inp)
    return out

input = torch.randn(2, dtype=torch.float16).cuda()

compiled_fn = torch.compile(toy_example, backend="inductor")

with torch.autograd.profiler.profile(use_cuda=True) as prof_eager:
   result_eager = toy_example(input)
print(prof_eager)
print(f"result_eager = {result_eager}")

result_compile = compiled_fn(input)
print(f"result_compile = {result_compile}")

The captured FX graph has the type promotion from fp16 to fp32, the ops sigmoid and mul is executed in fp32 and the result is converted back to fp16 before returning it -

def forward(self, arg0_1: "f16[2]"):
         # File: <ipython-input-9-a470008e5ba9>:9 in toy_example, code: out = m(inp)
         convert_element_type: "f32[2]" = torch.ops.prims.convert_element_type.default(arg0_1, torch.float32);  arg0_1 = None
         sigmoid: "f32[2]" = torch.ops.aten.sigmoid.default(convert_element_type)
         mul: "f32[2]" = torch.ops.aten.mul.Tensor(convert_element_type, sigmoid);  convert_element_type = sigmoid = None
         convert_element_type_1: "f16[2]" = torch.ops.prims.convert_element_type.default(mul, torch.float16);  mul = None
         return (convert_element_type_1,)

The eager execution profile doesn't show any type conversion -

-------------------------  ------------  ------------  ------------  ------------  ------------  ------------  ------------  ------------  ------------  ------------  
                     Name    Self CPU %      Self CPU   CPU total %     CPU total  CPU time avg     Self CUDA   Self CUDA %    CUDA total  CUDA time avg    # of Calls  
-------------------------  ------------  ------------  ------------  ------------  ------------  ------------  ------------  ------------  ------------  ------------  
          cudaEventRecord        13.33%      16.000us        13.33%      16.000us      16.000us       0.000us         0.00%       0.000us       0.000us             1  
               aten::silu        51.67%      62.000us        70.83%      85.000us      85.000us      95.000us       100.00%      95.000us      95.000us             1  
         cudaLaunchKernel        19.17%      23.000us        19.17%      23.000us      23.000us       0.000us         0.00%       0.000us       0.000us             1  
          cudaEventRecord         2.50%       3.000us         2.50%       3.000us       3.000us       0.000us         0.00%       0.000us       0.000us             1  
    cudaDeviceSynchronize        13.33%      16.000us        13.33%      16.000us      16.000us       0.000us         0.00%       0.000us       0.000us             1  
-------------------------  ------------  ------------  ------------  ------------  ------------  ------------  ------------  ------------  ------------  ------------  

Is there a reason torch.compile applies these type promotions as part of decomposition? It is a bit strange that if I include the op in decompositions passed to AOTAutograd, the dtype promotion is applied but if I don't use the decomposition, then the dtype promotion isn't applied on the op in the FX graph. The reason for this behavior isn't clear, it would be great to know the rationale behind this.

If a backend wants to apply the op decomposition and avoid the type promotions in FX , is there a way to do so other than overwriting these decompositions from the backend without the decorator?

Versions

PyTorch version: 2.3.0+cu118
Is debug build: False
CUDA used to build PyTorch: 11.8
ROCM used to build PyTorch: N/A

OS: Ubuntu 22.04.3 LTS (x86_64)
GCC version: (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0
Clang version: 14.0.0-1ubuntu1.1
CMake version: version 3.27.9
Libc version: glibc-2.35

Python version: 3.10.12 (main, Nov 20 2023, 15:14:05) [GCC 11.4.0] (64-bit runtime)
Python platform: Linux-6.1.58+-x86_64-with-glibc2.35
Is CUDA available: False
CUDA runtime version: 12.2.140
CUDA_MODULE_LOADING set to: N/A
GPU models and configuration: Could not collect
Nvidia driver version: Could not collect
cuDNN version: Probably one of the following:
/usr/lib/x86_64-linux-gnu/libcudnn.so.8.9.6
/usr/lib/x86_64-linux-gnu/libcudnn_adv_infer.so.8.9.6
/usr/lib/x86_64-linux-gnu/libcudnn_adv_train.so.8.9.6
/usr/lib/x86_64-linux-gnu/libcudnn_cnn_infer.so.8.9.6
/usr/lib/x86_64-linux-gnu/libcudnn_cnn_train.so.8.9.6
/usr/lib/x86_64-linux-gnu/libcudnn_ops_infer.so.8.9.6
/usr/lib/x86_64-linux-gnu/libcudnn_ops_train.so.8.9.6
HIP runtime version: N/A
MIOpen runtime version: N/A
Is XNNPACK available: True

CPU:
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Address sizes: 46 bits physical, 48 bits virtual
Byte Order: Little Endian
CPU(s): 2
On-line CPU(s) list: 0,1
Vendor ID: GenuineIntel
Model name: Intel(R) Xeon(R) CPU @ 2.20GHz
CPU family: 6
Model: 79
Thread(s) per core: 2
Core(s) per socket: 1
Socket(s): 1
Stepping: 0
BogoMIPS: 4399.99
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ss ht syscall nx pdpe1gb rdtscp lm constant_tsc rep_good nopl xtopology nonstop_tsc cpuid tsc_known_freq pni pclmulqdq ssse3 fma cx16 pcid sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand hypervisor lahf_lm abm 3dnowprefetch invpcid_single ssbd ibrs ibpb stibp fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm rdseed adx smap xsaveopt arat md_clear arch_capabilities
Hypervisor vendor: KVM
Virtualization type: full
L1d cache: 32 KiB (1 instance)
L1i cache: 32 KiB (1 instance)
L2 cache: 256 KiB (1 instance)
L3 cache: 55 MiB (1 instance)
NUMA node(s): 1
NUMA node0 CPU(s): 0,1
Vulnerability Gather data sampling: Not affected
Vulnerability Itlb multihit: Not affected
Vulnerability L1tf: Mitigation; PTE Inversion
Vulnerability Mds: Vulnerable; SMT Host state unknown
Vulnerability Meltdown: Vulnerable
Vulnerability Mmio stale data: Vulnerable
Vulnerability Retbleed: Vulnerable
Vulnerability Spec rstack overflow: Not affected
Vulnerability Spec store bypass: Vulnerable
Vulnerability Spectre v1: Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers
Vulnerability Spectre v2: Vulnerable, IBPB: disabled, STIBP: disabled, PBRSB-eIBRS: Not affected
Vulnerability Srbds: Not affected
Vulnerability Tsx async abort: Vulnerable

Versions of relevant libraries:
[pip3] numpy==1.26.3
[pip3] torch==2.3.0+cu118
[pip3] torchaudio==2.3.0+cu118
[pip3] torchdata==0.7.1
[pip3] torchsummary==1.5.1
[pip3] torchtext==0.17.1
[pip3] torchvision==0.18.0+cu118
[pip3] triton==2.3.0
[conda] Could not collect

cc @nairbv @mruberry @ezyang @msaroufim @bdhirsh @anijain2305 @chauhang @SherlockNoMad @voznesenskym @penguinwu @EikanWang @jgong5 @Guobing-Chen @XiaobingSuper @zhuhaozhe @blzheng @wenzhe-nrv @jiayisunx @peterbell10 @ipiszy @yf225 @chenyang78 @kadeng @muchulee8 @ColinPeppler @amjames @desertfire

[ezyang]

In eager, the promotion is fused into the kernel. When we do decompositions, we are unfusing all of these things, and part of that is taking the operation to the computation type before doing a series of operations. If we did not do that, we would, e.g., accumulate a lot of error doing float16 operations when in the real kernel it was done in float32 precision.

As for if you're a custom backend that wants to avoid this promotion, there is not an easy way, I'm afraid. Maybe we could add a flag to globally turn off the promotions, but NGL, I don't think you actually want this.

[sujoysaraswati]

I had thought the decomposed ops (in the example of silu, there is sigmoid and mul) will decide the type promotion inside the kernel. As you mentioned, without the decomposition, silu does the type promotion inside the kernel using opmath. Similarly, sigmoid also does a type promotion inside the kernel using opmath. Once silu is decomposed, will it not be sufficient to let the sigmoid kernel do the type promotion inside the kernel, instead of the type promotion across the decomposed ops?
With the decomposition and pw_cast_for_opmath applied at FX level, the type promotions are now explicitly done as different ops outside the kernel. The concern is whether this will increase the device time.

[ezyang]

I mean, if you decompose sigmoid, there's no "kernel to do type promotion" inside of, you don't have a sigmoid anymore!

Yes, the extra casts will make a direct eager executor slower. But, you know, decomposing sigmoid will also make your eager executor slower. If you have a compiler, then it's not a problem.

[sujoysaraswati]

I was assuming the decomposition will stop at sigmoid because it is a core ATen op, but you are possibly right it is safer for silu decomposition to add the type promotion instead of understanding whether it is decomposing into core ATen ops that has the type promotion logic in kernel.

[peterbell10]

Even if sigmoid is not decomposed, we need the computation dtype to prevent sigmoid(self) being rounded to half precision before the multiplication happens.

[sujoysaraswati]

Thanks, closing it as this is a required promotion in the decomposition logic.