GitHub - Chanartip/CECS360: Integrated_Circuit_Design class at CSULB

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Integrated_Circuit_Design class at CSULB

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Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
AISO_rst.v		AISO_rst.v
Counter.v		Counter.v
Counter_on_7seg.v		Counter_on_7seg.v
Debounce.v		Debounce.v
Debounce_tb.v		Debounce_tb.v
Mux4to1.v		Mux4to1.v
PED.v		PED.v
Project1_ucf.ucf		Project1_ucf.ucf
SSG_Driver.v		SSG_Driver.v
Tick_Gen_10ms.v		Tick_Gen_10ms.v
Tick_Gen_6ms.v		Tick_Gen_6ms.v
hex_to7segment.v		hex_to7segment.v
led_controller.v		led_controller.v

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Integrated_Circuit_Design class at CSULB

counter verilog 7-segment debounce-button uphdl clockdivider

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Verilog 100.0%